Introduction

Verification is the designer’s nightmare!

The verification cost goes up to 70% from complete design cost. The error detection and correction at system level are, in loss of income, 20000 times less expensive than at circuit level.

Cost of system verification
Source:Integrated Communications Design May, 2001

Some design specification errors might never even be detected if the verification process starts below the system level, because they concern the global properties, which can be expressed only at that level. Some design errors are not detected before the actual use of the product. That brings enormous cost, even death of the product.

We give you a solution:

KeesDA wants to bring a major technological step by creating a new verification solution that
▪ uses formal methods for ESL.
▪ produces correct by construction HW and SW
▪ integrates itself into the existing design flow